drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

730

#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

705

#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

708

#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2537

#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

867

#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

5248

#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

5074

#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

4652

#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L