drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1536

#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1539

#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2977

#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2073

#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6355

#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7159

#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6182

#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

5359

#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

808

#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT 0x0