drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1537

#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1540

#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2978

#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2074

#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6356

#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7160

#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6183

#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

5360

#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

809

#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT 0x4