drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

936

#define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

939

#define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

1506

#define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

1132

#define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

5395

#define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

6111

#define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

5216

#define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

4941

#define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

6811

#define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x2