drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1237

#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1240

#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

1973

#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

1588

#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

5851

#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

6209

#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

5672

#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

5011

#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

6881

#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT 0x8