drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

293

#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x2000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

226

#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

293

#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x2000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

317

#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x2000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

319

#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x2000

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

2006

#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2054

#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3725

#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2784

#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

3902

#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

3937

#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

3768

#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

3458

#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

4950

#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L