drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

108

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1570

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1573

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3011

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2119

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6400

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7216

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6233

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

5410

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

865

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L