drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

104

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1566

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1569

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3007

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2115

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6396

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7212

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6229

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

5406

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

861

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2