drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

109

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1571

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1574

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3012

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2120

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6401

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7217

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6234

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

5411

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

866

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L