drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

99

#define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1555

#define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1558

#define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2996

#define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2104

#define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6385

#define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7201

#define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6218

#define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

5395

#define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

850

#define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L