drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

95

#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1551

#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1554

#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2992

#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2100

#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6381

#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7197

#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6214

#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

5391

#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

846

#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0xe