drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

157

#define UVD_CGC_GATE__WCB_MASK 0x20000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

116

#define UVD_CGC_GATE__WCB_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

157

#define UVD_CGC_GATE__WCB_MASK 0x20000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

169

#define UVD_CGC_GATE__WCB_MASK 0x20000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

171

#define UVD_CGC_GATE__WCB_MASK 0x20000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

414

#define UVD_CGC_GATE__WCB_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

842

#define UVD_CGC_GATE__WCB_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1861

#define UVD_CGC_GATE__WCB_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1912

#define UVD_CGC_GATE__WCB_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3583

#define UVD_CGC_GATE__WCB_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2642

#define UVD_CGC_GATE__WCB_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

77

#define UVD_CGC_GATE__WCB_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

77

#define UVD_CGC_GATE__WCB_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

73

#define UVD_CGC_GATE__WCB_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

77

#define UVD_CGC_GATE__WCB_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1428

#define UVD_CGC_GATE__WCB_MASK 0x00020000L