drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

159

#define UVD_CGC_GATE__VCPU_MASK 0x40000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

114

#define UVD_CGC_GATE__VCPU_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

159

#define UVD_CGC_GATE__VCPU_MASK 0x40000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

171

#define UVD_CGC_GATE__VCPU_MASK 0x40000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

173

#define UVD_CGC_GATE__VCPU_MASK 0x40000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

415

#define UVD_CGC_GATE__VCPU_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

843

#define UVD_CGC_GATE__VCPU_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1862

#define UVD_CGC_GATE__VCPU_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1913

#define UVD_CGC_GATE__VCPU_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3584

#define UVD_CGC_GATE__VCPU_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2643

#define UVD_CGC_GATE__VCPU_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

78

#define UVD_CGC_GATE__VCPU_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

78

#define UVD_CGC_GATE__VCPU_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

74

#define UVD_CGC_GATE__VCPU_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

78

#define UVD_CGC_GATE__VCPU_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1429

#define UVD_CGC_GATE__VCPU_MASK 0x00040000L