drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

148

#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

112

#define UVD_CGC_GATE__UDEC_RE__SHIFT 0x0000000c

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

148

#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

160

#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

162

#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

389

#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

817

#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1835

#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1887

#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3558

#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2617

#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

46

#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

46

#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

42

#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

46

#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1394

#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc