drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

147

#define UVD_CGC_GATE__UDEC_RE_MASK 0x1000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

111

#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

147

#define UVD_CGC_GATE__UDEC_RE_MASK 0x1000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

159

#define UVD_CGC_GATE__UDEC_RE_MASK 0x1000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

161

#define UVD_CGC_GATE__UDEC_RE_MASK 0x1000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

409

#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

837

#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1856

#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1907

#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3578

#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2637

#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

72

#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

72

#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

68

#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

72

#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1423

#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L