drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

125

#define UVD_CGC_GATE__UDEC_MASK 0x2

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

108

#define UVD_CGC_GATE__UDEC_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

125

#define UVD_CGC_GATE__UDEC_MASK 0x2

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

137

#define UVD_CGC_GATE__UDEC_MASK 0x2

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

139

#define UVD_CGC_GATE__UDEC_MASK 0x2

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

398

#define UVD_CGC_GATE__UDEC_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

826

#define UVD_CGC_GATE__UDEC_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1845

#define UVD_CGC_GATE__UDEC_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1896

#define UVD_CGC_GATE__UDEC_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3567

#define UVD_CGC_GATE__UDEC_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2626

#define UVD_CGC_GATE__UDEC_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

61

#define UVD_CGC_GATE__UDEC_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

61

#define UVD_CGC_GATE__UDEC_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

57

#define UVD_CGC_GATE__UDEC_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

61

#define UVD_CGC_GATE__UDEC_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1412

#define UVD_CGC_GATE__UDEC_MASK 0x00000002L