drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

152

#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

107

#define UVD_CGC_GATE__UDEC_IT__SHIFT 0x0000000e

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

152

#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

164

#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

166

#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

391

#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

819

#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1837

#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1889

#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3560

#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2619

#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

48

#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

48

#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

44

#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

48

#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1396

#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe