drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

151

#define UVD_CGC_GATE__UDEC_IT_MASK 0x4000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

106

#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

151

#define UVD_CGC_GATE__UDEC_IT_MASK 0x4000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

163

#define UVD_CGC_GATE__UDEC_IT_MASK 0x4000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

165

#define UVD_CGC_GATE__UDEC_IT_MASK 0x4000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

411

#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

839

#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1858

#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1909

#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3580

#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2639

#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

74

#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

74

#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

70

#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

74

#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1425

#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L