drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

153

#define UVD_CGC_GATE__UDEC_DB_MASK 0x8000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

104

#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

153

#define UVD_CGC_GATE__UDEC_DB_MASK 0x8000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

165

#define UVD_CGC_GATE__UDEC_DB_MASK 0x8000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

167

#define UVD_CGC_GATE__UDEC_DB_MASK 0x8000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

412

#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

840

#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1859

#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1910

#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3581

#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2640

#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

75

#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

75

#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

71

#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

75

#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1426

#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L