drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

150

#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

103

#define UVD_CGC_GATE__UDEC_CM__SHIFT 0x0000000d

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

150

#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

162

#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

164

#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

390

#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

818

#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1836

#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1888

#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3559

#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2618

#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

47

#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

47

#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

43

#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

47

#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1395

#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd