drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

149

#define UVD_CGC_GATE__UDEC_CM_MASK 0x2000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

102

#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

149

#define UVD_CGC_GATE__UDEC_CM_MASK 0x2000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

161

#define UVD_CGC_GATE__UDEC_CM_MASK 0x2000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

163

#define UVD_CGC_GATE__UDEC_CM_MASK 0x2000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

410

#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

838

#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1857

#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1908

#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3579

#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2638

#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

73

#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

73

#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

69

#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

73

#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1424

#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L