drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

123

#define UVD_CGC_GATE__SYS_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

100

#define UVD_CGC_GATE__SYS_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

123

#define UVD_CGC_GATE__SYS_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

135

#define UVD_CGC_GATE__SYS_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

137

#define UVD_CGC_GATE__SYS_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

397

#define UVD_CGC_GATE__SYS_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

825

#define UVD_CGC_GATE__SYS_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1844

#define UVD_CGC_GATE__SYS_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1895

#define UVD_CGC_GATE__SYS_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3566

#define UVD_CGC_GATE__SYS_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2625

#define UVD_CGC_GATE__SYS_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

60

#define UVD_CGC_GATE__SYS_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

60

#define UVD_CGC_GATE__SYS_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

56

#define UVD_CGC_GATE__SYS_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

60

#define UVD_CGC_GATE__SYS_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1411

#define UVD_CGC_GATE__SYS_MASK 0x00000001L