Symbol: UVD_CGC_GATE__REGS__SHIFT
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h
130
#define UVD_CGC_GATE__REGS__SHIFT 0x3
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h
97
#define UVD_CGC_GATE__REGS__SHIFT 0x00000003
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h
130
#define UVD_CGC_GATE__REGS__SHIFT 0x3
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h
142
#define UVD_CGC_GATE__REGS__SHIFT 0x3
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h
144
#define UVD_CGC_GATE__REGS__SHIFT 0x3
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h
380
#define UVD_CGC_GATE__REGS__SHIFT 0x3
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
808
#define UVD_CGC_GATE__REGS__SHIFT 0x3
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h
1826
#define UVD_CGC_GATE__REGS__SHIFT 0x3
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h
1878
#define UVD_CGC_GATE__REGS__SHIFT 0x3
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h
3549
#define UVD_CGC_GATE__REGS__SHIFT 0x3
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h
2608
#define UVD_CGC_GATE__REGS__SHIFT 0x3
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h
37
#define UVD_CGC_GATE__REGS__SHIFT 0x3
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h
37
#define UVD_CGC_GATE__REGS__SHIFT 0x3
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h
33
#define UVD_CGC_GATE__REGS__SHIFT 0x3
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h
37
#define UVD_CGC_GATE__REGS__SHIFT 0x3
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h
1385
#define UVD_CGC_GATE__REGS__SHIFT 0x3