drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

129

#define UVD_CGC_GATE__REGS_MASK 0x8

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

96

#define UVD_CGC_GATE__REGS_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

129

#define UVD_CGC_GATE__REGS_MASK 0x8

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

141

#define UVD_CGC_GATE__REGS_MASK 0x8

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

143

#define UVD_CGC_GATE__REGS_MASK 0x8

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

400

#define UVD_CGC_GATE__REGS_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

828

#define UVD_CGC_GATE__REGS_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1847

#define UVD_CGC_GATE__REGS_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1898

#define UVD_CGC_GATE__REGS_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3569

#define UVD_CGC_GATE__REGS_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2628

#define UVD_CGC_GATE__REGS_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

63

#define UVD_CGC_GATE__REGS_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

63

#define UVD_CGC_GATE__REGS_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

59

#define UVD_CGC_GATE__REGS_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

63

#define UVD_CGC_GATE__REGS_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1414

#define UVD_CGC_GATE__REGS_MASK 0x00000008L