drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

131

#define UVD_CGC_GATE__RBC_MASK 0x10

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

94

#define UVD_CGC_GATE__RBC_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

131

#define UVD_CGC_GATE__RBC_MASK 0x10

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

143

#define UVD_CGC_GATE__RBC_MASK 0x10

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

145

#define UVD_CGC_GATE__RBC_MASK 0x10

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

401

#define UVD_CGC_GATE__RBC_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

829

#define UVD_CGC_GATE__RBC_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1848

#define UVD_CGC_GATE__RBC_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1899

#define UVD_CGC_GATE__RBC_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3570

#define UVD_CGC_GATE__RBC_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2629

#define UVD_CGC_GATE__RBC_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

64

#define UVD_CGC_GATE__RBC_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

64

#define UVD_CGC_GATE__RBC_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

60

#define UVD_CGC_GATE__RBC_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

64

#define UVD_CGC_GATE__RBC_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1415

#define UVD_CGC_GATE__RBC_MASK 0x00000010L