drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

140

#define UVD_CGC_GATE__MPRD__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

93

#define UVD_CGC_GATE__MPRD__SHIFT 0x00000008

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

140

#define UVD_CGC_GATE__MPRD__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

152

#define UVD_CGC_GATE__MPRD__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

154

#define UVD_CGC_GATE__MPRD__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

385

#define UVD_CGC_GATE__MPRD__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

813

#define UVD_CGC_GATE__MPRD__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1831

#define UVD_CGC_GATE__MPRD__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1883

#define UVD_CGC_GATE__MPRD__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3554

#define UVD_CGC_GATE__MPRD__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2613

#define UVD_CGC_GATE__MPRD__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

42

#define UVD_CGC_GATE__MPRD__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

42

#define UVD_CGC_GATE__MPRD__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

38

#define UVD_CGC_GATE__MPRD__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

42

#define UVD_CGC_GATE__MPRD__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1390

#define UVD_CGC_GATE__MPRD__SHIFT 0x8