drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

139

#define UVD_CGC_GATE__MPRD_MASK 0x100

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

92

#define UVD_CGC_GATE__MPRD_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

139

#define UVD_CGC_GATE__MPRD_MASK 0x100

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

151

#define UVD_CGC_GATE__MPRD_MASK 0x100

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

153

#define UVD_CGC_GATE__MPRD_MASK 0x100

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

405

#define UVD_CGC_GATE__MPRD_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

833

#define UVD_CGC_GATE__MPRD_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1852

#define UVD_CGC_GATE__MPRD_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1903

#define UVD_CGC_GATE__MPRD_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3574

#define UVD_CGC_GATE__MPRD_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2633

#define UVD_CGC_GATE__MPRD_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

68

#define UVD_CGC_GATE__MPRD_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

68

#define UVD_CGC_GATE__MPRD_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

64

#define UVD_CGC_GATE__MPRD_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

68

#define UVD_CGC_GATE__MPRD_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1419

#define UVD_CGC_GATE__MPRD_MASK 0x00000100L