drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

127

#define UVD_CGC_GATE__MPEG2_MASK 0x4

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

90

#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

127

#define UVD_CGC_GATE__MPEG2_MASK 0x4

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

139

#define UVD_CGC_GATE__MPEG2_MASK 0x4

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

141

#define UVD_CGC_GATE__MPEG2_MASK 0x4

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

399

#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

827

#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1846

#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1897

#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3568

#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2627

#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

62

#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

62

#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

58

#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

62

#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1413

#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L