drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

141

#define UVD_CGC_GATE__MPC_MASK 0x200

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

88

#define UVD_CGC_GATE__MPC_MASK 0x00000200L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

141

#define UVD_CGC_GATE__MPC_MASK 0x200

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

153

#define UVD_CGC_GATE__MPC_MASK 0x200

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

155

#define UVD_CGC_GATE__MPC_MASK 0x200

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

406

#define UVD_CGC_GATE__MPC_MASK 0x00000200L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

834

#define UVD_CGC_GATE__MPC_MASK 0x00000200L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1853

#define UVD_CGC_GATE__MPC_MASK 0x00000200L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1904

#define UVD_CGC_GATE__MPC_MASK 0x00000200L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3575

#define UVD_CGC_GATE__MPC_MASK 0x00000200L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2634

#define UVD_CGC_GATE__MPC_MASK 0x00000200L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

69

#define UVD_CGC_GATE__MPC_MASK 0x00000200L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

69

#define UVD_CGC_GATE__MPC_MASK 0x00000200L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

65

#define UVD_CGC_GATE__MPC_MASK 0x00000200L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

69

#define UVD_CGC_GATE__MPC_MASK 0x00000200L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1420

#define UVD_CGC_GATE__MPC_MASK 0x00000200L