drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1864

#define UVD_CGC_GATE__MMSCH_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1914

#define UVD_CGC_GATE__MMSCH_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3585

#define UVD_CGC_GATE__MMSCH_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2644

#define UVD_CGC_GATE__MMSCH_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

79

#define UVD_CGC_GATE__MMSCH_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

79

#define UVD_CGC_GATE__MMSCH_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

75

#define UVD_CGC_GATE__MMSCH_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

79

#define UVD_CGC_GATE__MMSCH_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1430

#define UVD_CGC_GATE__MMSCH_MASK 0x00100000L