drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

146

#define UVD_CGC_GATE__LRBBM__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

87

#define UVD_CGC_GATE__LRBBM__SHIFT 0x0000000b

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

146

#define UVD_CGC_GATE__LRBBM__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

158

#define UVD_CGC_GATE__LRBBM__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

160

#define UVD_CGC_GATE__LRBBM__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

388

#define UVD_CGC_GATE__LRBBM__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

816

#define UVD_CGC_GATE__LRBBM__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1834

#define UVD_CGC_GATE__LRBBM__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1886

#define UVD_CGC_GATE__LRBBM__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3557

#define UVD_CGC_GATE__LRBBM__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2616

#define UVD_CGC_GATE__LRBBM__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

45

#define UVD_CGC_GATE__LRBBM__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

45

#define UVD_CGC_GATE__LRBBM__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

41

#define UVD_CGC_GATE__LRBBM__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

45

#define UVD_CGC_GATE__LRBBM__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1393

#define UVD_CGC_GATE__LRBBM__SHIFT 0xb