drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

145

#define UVD_CGC_GATE__LRBBM_MASK 0x800

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

86

#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

145

#define UVD_CGC_GATE__LRBBM_MASK 0x800

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

157

#define UVD_CGC_GATE__LRBBM_MASK 0x800

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

159

#define UVD_CGC_GATE__LRBBM_MASK 0x800

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

408

#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

836

#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1855

#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1906

#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3577

#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2636

#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

71

#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

71

#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

67

#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

71

#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1422

#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L