drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

136

#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

85

#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x00000006

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

136

#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

148

#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

150

#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

383

#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

811

#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1829

#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1881

#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3552

#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2611

#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

40

#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

40

#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

36

#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

40

#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1388

#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6