drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

135

#define UVD_CGC_GATE__LMI_UMC_MASK 0x40

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

84

#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

135

#define UVD_CGC_GATE__LMI_UMC_MASK 0x40

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

147

#define UVD_CGC_GATE__LMI_UMC_MASK 0x40

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

149

#define UVD_CGC_GATE__LMI_UMC_MASK 0x40

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

403

#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

831

#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1850

#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1901

#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3572

#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2631

#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

66

#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

66

#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

62

#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

66

#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1417

#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L