drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

133

#define UVD_CGC_GATE__LMI_MC_MASK 0x20

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

82

#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

133

#define UVD_CGC_GATE__LMI_MC_MASK 0x20

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

145

#define UVD_CGC_GATE__LMI_MC_MASK 0x20

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

147

#define UVD_CGC_GATE__LMI_MC_MASK 0x20

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

402

#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

830

#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1849

#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1900

#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3571

#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2630

#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

65

#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

65

#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

61

#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

65

#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1416

#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L