drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

144

#define UVD_CGC_GATE__LBSI__SHIFT 0xa

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

81

#define UVD_CGC_GATE__LBSI__SHIFT 0x0000000a

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

144

#define UVD_CGC_GATE__LBSI__SHIFT 0xa

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

156

#define UVD_CGC_GATE__LBSI__SHIFT 0xa

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

158

#define UVD_CGC_GATE__LBSI__SHIFT 0xa

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

387

#define UVD_CGC_GATE__LBSI__SHIFT 0xa

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

815

#define UVD_CGC_GATE__LBSI__SHIFT 0xa

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1833

#define UVD_CGC_GATE__LBSI__SHIFT 0xa

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1885

#define UVD_CGC_GATE__LBSI__SHIFT 0xa

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3556

#define UVD_CGC_GATE__LBSI__SHIFT 0xa

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2615

#define UVD_CGC_GATE__LBSI__SHIFT 0xa

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

44

#define UVD_CGC_GATE__LBSI__SHIFT 0xa

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

44

#define UVD_CGC_GATE__LBSI__SHIFT 0xa

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

40

#define UVD_CGC_GATE__LBSI__SHIFT 0xa

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

44

#define UVD_CGC_GATE__LBSI__SHIFT 0xa

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1392

#define UVD_CGC_GATE__LBSI__SHIFT 0xa