drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

143

#define UVD_CGC_GATE__LBSI_MASK 0x400

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

80

#define UVD_CGC_GATE__LBSI_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

143

#define UVD_CGC_GATE__LBSI_MASK 0x400

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

155

#define UVD_CGC_GATE__LBSI_MASK 0x400

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

157

#define UVD_CGC_GATE__LBSI_MASK 0x400

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

407

#define UVD_CGC_GATE__LBSI_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

835

#define UVD_CGC_GATE__LBSI_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1854

#define UVD_CGC_GATE__LBSI_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1905

#define UVD_CGC_GATE__LBSI_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3576

#define UVD_CGC_GATE__LBSI_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2635

#define UVD_CGC_GATE__LBSI_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

70

#define UVD_CGC_GATE__LBSI_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

70

#define UVD_CGC_GATE__LBSI_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

66

#define UVD_CGC_GATE__LBSI_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

70

#define UVD_CGC_GATE__LBSI_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1421

#define UVD_CGC_GATE__LBSI_MASK 0x00000400L