drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

137

#define UVD_CGC_GATE__IDCT_MASK 0x80

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

78

#define UVD_CGC_GATE__IDCT_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

137

#define UVD_CGC_GATE__IDCT_MASK 0x80

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

149

#define UVD_CGC_GATE__IDCT_MASK 0x80

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

151

#define UVD_CGC_GATE__IDCT_MASK 0x80

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

404

#define UVD_CGC_GATE__IDCT_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

832

#define UVD_CGC_GATE__IDCT_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1851

#define UVD_CGC_GATE__IDCT_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1902

#define UVD_CGC_GATE__IDCT_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3573

#define UVD_CGC_GATE__IDCT_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2632

#define UVD_CGC_GATE__IDCT_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

67

#define UVD_CGC_GATE__IDCT_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

67

#define UVD_CGC_GATE__IDCT_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

63

#define UVD_CGC_GATE__IDCT_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

67

#define UVD_CGC_GATE__IDCT_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1418

#define UVD_CGC_GATE__IDCT_MASK 0x00000080L