drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

262

#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

77

#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x0000001c

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

262

#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

284

#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

286

#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

438

#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

931

#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1949

#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1999

#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3670

#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2729

#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

107

#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

107

#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

103

#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

107

#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1461

#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c