drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

261

#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

76

#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

261

#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

283

#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

285

#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

461

#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

954

#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1973

#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2022

#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3693

#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2752

#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

130

#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

130

#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

126

#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

130

#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1484

#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L