drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

263

#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

74

#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

263

#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

285

#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

287

#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

462

#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

955

#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1974

#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2023

#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3694

#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2753

#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

131

#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

131

#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

127

#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

131

#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1485

#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L