drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

228

#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

73

#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0x0000000b

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

228

#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

250

#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

252

#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

421

#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

914

#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1932

#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1982

#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3653

#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2712

#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

90

#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

90

#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

86

#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

90

#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1444

#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb