drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

227

#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

72

#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

227

#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

249

#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

251

#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

444

#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

937

#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1956

#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2005

#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3676

#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2735

#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

113

#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

113

#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

109

#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

113

#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1467

#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L