drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

236

#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

71

#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0x0000000f

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

236

#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

258

#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

260

#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

425

#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

918

#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1936

#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1986

#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3657

#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2716

#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

94

#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

94

#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

90

#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

94

#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1448

#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf