drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

235

#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

70

#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

235

#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

257

#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

259

#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

448

#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

941

#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1960

#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2009

#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3680

#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2739

#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

117

#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

117

#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

113

#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

117

#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1471

#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L