drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

240

#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

69

#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x00000011

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

240

#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

262

#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

264

#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

427

#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

920

#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1938

#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1988

#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3659

#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2718

#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

96

#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

96

#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

92

#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

96

#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1450

#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11