drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

239

#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x20000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

68

#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

239

#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x20000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

261

#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x20000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

263

#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x20000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

450

#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

943

#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1962

#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2011

#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3682

#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2741

#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

119

#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

119

#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

115

#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

119

#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1473

#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L