Symbol: UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h
232
#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h
67
#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0x0000000d
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h
232
#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h
254
#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h
256
#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h
423
#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
916
#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h
1934
#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h
1984
#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h
3655
#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h
2714
#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h
92
#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h
92
#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h
88
#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h
92
#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h
1446
#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd