drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

231

#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

66

#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

231

#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

253

#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

255

#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

446

#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

939

#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1958

#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2007

#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3678

#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2737

#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

115

#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

115

#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

111

#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

115

#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1469

#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L