Symbol: UVD_CGC_CTRL__UDEC_DB_MODE_MASK
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h
233
#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h
64
#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h
233
#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h
255
#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h
257
#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h
447
#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
940
#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h
1959
#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h
2008
#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h
3679
#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h
2738
#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h
116
#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h
116
#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h
112
#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h
116
#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h
1470
#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L